In an MOS static random access memory (SRAM), a data bit of a memory cell is typically read and written by a signal represented as a differential voltage between two bit lines. Multiple memory cells are coupled to one bit line pair and form a column of the memory, with each memory cell located on one row of the column. Each memory cell has a unique address at an intersection of a row and a column. The bit line pairs are commonly used for both reading data from and writing data to the memory cell. When a write cycle occurs, the data bit is driven onto the bit line pair as a differential voltage between the two bit lines. The differential voltage is large enough to overwrite an existing value in the selected memory cell. Typically the differential voltage on the bit lines during the write cycle is approximately 3 volts. When a read cycle takes place, a selected memory cell places a data bit stored within the selected memory cell on the bit line pairs differentially also, but the differential voltage for the read cycle is relatively small and may be below 100 millivolts.
When a write cycle is completed, a read cycle begins, and the differential voltage remaining on the bit line pair at the end of the write cycle must be reduced to a level low enough so that the data is not erroneously written into a memory during the ensuing read cycle. The differential voltage on the bit line pair must also be reduced quickly so that the read cycle is not unnecessarily extended. This process is called write recovery. Write recovery may include either coupling a first bit line of a bit line pair to a second bit line of the bit line pair so that their voltages will approach each other (known as equalization), or coupling both lines to a reference voltage, commonly a 5-volt power supply voltage terminal V.sub.DD (known as precharging), or both. However achieved, write recovery must make the voltages on the first and second bit lines of the bit line pair close enough so that data is not overwritten and that the correct data is sensed quickly during the read cycle.
Write recovery is typically achieved by circuits known as bit line loads, which are coupled to each bit line pair. At the termination of the write cycle the bit line loads either couple the first bit line to the second bit line of the bit line pairs, or coupled each bit line to a power supply voltage terminal such as V.sub.DD, or both. A data bit to be written onto the bit line pair during a write cycle may also be provided through the bit line load. In this case, the bit line load also functions as a write gate. If bipolar-CMOS (BICMOS) technology is available, bipolar transistors, which are faster than corresponding CMOS transistors, may be used to precharge corresponding bit line pairs and to provide the write voltages.
Several problems are encountered in the design of a BICMOS bit line load and write gate. During the write cycle, the relatively large differential signal provided on the bit lines in order to overwrite the contents of a selected memory cell may exceed 3 volts. If a biasing signal provided to the bases of the bipolar transistors in the bit line loads is at a logic low when the emitters, coupled to the bit lines, are at a logic high, a large reverse bias may be developed on the base-emitter junctions of the bipolar transistors. Bipolar transistors degrade in the reverse biased condition and as reverse bias increases, the amount of degradation increases. Therefore using bipolar transistors is subject to reliability problems in that the transistors may degrade over time, ultimately resulting in a failure of the memory. Often the solution of the reliability problem creates other problems which must also be addressed.